This invention relates to programmable logic devices, and more particularly to the logic modules used in such devices.
Many programmable logic devices include logic modules (also sometimes called logic elements) that are basically programmable look-up tables. See, for example, Cliff et al. U.S. Pat. No. 5,260,611, Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. patent application Ser. No. 09/266,235, filed Mar. 10, 1999, and Ngai et al. U.S. patent application Ser. No. 09/516,921, filed Mar. 2, 2000. It is known to construct such logic modules so that the programmable memory bits and associated circuitry in a module can have other uses, e.g., to provide dynamic memory or shift register capabilities. See, for example, Freeman et al. U.S. Pat. No. 5,343,406, Freidin et al. U.S. Pat. No. 5,566,123, and Bauer U.S. Pat. No. 5,889,413. In some uses of programmable logic devices, however, normal shift registers may have various short-comings, and rapid clearing of the known shift registers in logic modules may not be convenient or possible.
In accordance with the present invention the look-up table circuitry in a logic module of a programmable logic device is additionally provided with a separate shift register. The output selection control circuitry of the look-up table (or similar but separate selection control circuitry) is used to select and read out the contents of any desired shift register stage. The shift register stages are preferably coupled to the output selection control circuitry in a pattern which facilitates using a Gray code to read the contents of the shift register. All stages of the shift register are preferably clearable in parallel using a single clear signal. The shift registers in two logic modules may be cascaded together to facilitate the provision of longer shift registers.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.